Traccia Schedino ADC-DAC

[Lupo]

Qualcuno ha svolto questa traccia?
Traccia per F3
Configurare il DAC per generare una tensione sinusoidale di ampiezza pari a 1000 cod., offset pari a 2048 e periodo (espresso in ms) pari al secondo numero XXXX della matricola (NYY/XXXX). Si utilizzino 200 campioni per rappresentare un periodo. La generazione deve essere temporizzata con trigger del timer e l’aggiornamento del campione da generare mediante DMA.
Campionare tale segnale con l'ADC facendo in modo da avere 73 campioni per ogni periodo di sx ed acquisirne 15 periodi in un opportuno array. L’avvio della conversione ed il salvataggio nell’array devono essere eseguite in interrupt del Timer e dell’ADC, rispettivamente.
Sui campioni acquisiti valutare il valore efficace ed il periodo della sola componente sinusoidale (senza offset).

 

[John_Frusciante]

#include<stm32f30x.h>
#include<math.h>
#include<stdio.h>
#define N 200
#define DIM_ADC 73*15
#define PI 3.1415
#define fck 72*pow(10,6)

short int LUT[N];
short int vett[DIM_ADC];

int j=0;
int ampiezza=1000;
const int offset=2048;
float V=0;

void abilitaPerif();
void setupDAC();
void setupADC();
void setupDMA_ADC();
void setupDMA_DAC();
void setupTIM2();
void GeneraSin();

void  main()
{
  GeneraSin();
  abilitaPerif();
  setupDMA_ADC();
  setupDMA_DAC();
  setupADC();
  setupDAC();
  setupTIM2();



  while(1);
}

void GeneraSin(){
  for(int i=0;i<N;i++){
    V=offset+(sin((2*PI*i)/N)*ampiezza);
    LUT[i]=(short int )(V);
  }
}
void abilitaPerif(){
  RCC->AHBENR|=RCC_AHBENR_GPIOAEN;
  RCC->APB1ENR|=RCC_APB1ENR_TIM2EN;
  RCC->AHBENR|=RCC_AHBENR_ADC12EN;
  RCC->APB1ENR|=RCC_APB1ENR_DACEN;
  RCC->AHBENR|=RCC_AHBENR_DMA1EN;
  RCC->AHBENR|=RCC_AHBENR_DMA2EN;


  GPIOA->MODER|=GPIO_MODER_MODER2;//MOD. ANALOGICA PA2
  GPIOA->MODER|=GPIO_MODER_MODER4;//MOD.ANALOGICA PA4

}
void setupTIM2(){
  TIM2->DIER|=TIM_DIER_UIE;//
  NVIC->ISER[0]|=(1<<28);//QUI ABILITO INTERRUPT TIM2;

  TIM2->CNT=0;
  TIM2->ARR=2046700;//matricola*FCK
  TIM2->CR2|=TIM_CR2_MMS_1;
  TIM2->CR1|=TIM_CR1_CEN;
}
void setupDMA_ADC(){
  DMA1_Channel1->CMAR=(uint32_t)vett;
  DMA1_Channel1->CPAR=(uint32_t)&ADC1->DR;
  DMA1_Channel1->CNDTR=DIM_ADC;
  DMA1_Channel1->CCR|=DMA_CCR_MSIZE_0;
  DMA1_Channel1->CCR|=DMA_CCR_PSIZE_0;
  DMA1_Channel1->CCR|=DMA_CCR_MINC;
  DMA1_Channel1->CCR&=~DMA_CCR_DIR;

}
void setupDMA_DAC(){
  DMA2_Channel3->CMAR=(uint32_t)LUT;
  DMA2_Channel3->CPAR=(uint32_t)&DAC->DHR12R1;
  DMA2_Channel3->CNDTR=N;
  DMA2_Channel3->CCR|=DMA_CCR_MSIZE_0;
  DMA2_Channel3->CCR|=DMA_CCR_PSIZE_0;
  DMA2_Channel3->CCR|=DMA_CCR_MINC;
    DMA2_Channel3->CCR|=DMA_CCR_CIRC;

  DMA2_Channel3->CCR|=DMA_CCR_DIR;
  DMA2_Channel3->CCR|=DMA_CCR_EN;

}
void setupADC(){
  ADC1->CR&=~ADC_CR_ADVREGEN_1;
  ADC1->CR|=ADC_CR_ADVREGEN_0;
  for(int i=0;i<1000;i++);

  ADC1_2->CCR|=ADC12_CCR_CKMODE_0;

  ADC1->CR|=ADC_CR_ADCAL;
  while(  (ADC1->CR&ADC_CR_ADCAL)==ADC_CR_ADCAL);

  ADC1->CR|=ADC_CR_ADEN;
  while((ADC1->CR&ADC_ISR_ADRD)!=ADC_ISR_ADRD);

  ADC1->IER|=ADC_IER_EOC;
  NVIC->ISER[0]|=1<<18;
  ADC1->CFGR|=ADC_CFGR_DMAEN;
  /*ADC1->CFGR|=ADC_CFGR_EXTEN_0;
  ADC1->CFGR|=11<<6;
*/
  ADC1->CFGR&=~ADC_CFGR_CONT;
  ADC1->SQR1&=~ADC_SQR1_L;
  ADC1->SQR1|=3<<6;
  ADC1->SMPR1|=ADC_SMPR1_SMP3;
}
void setupDAC(){
  DAC->CR|=DAC_CR_DMAEN1;
  DAC->CR|=DAC_CR_TEN1;
  DAC->CR|=DAC_CR_TSEL1_2;

  DAC->CR|=DAC_CR_EN1;

}
void TIM2_IRQHandler(){
    printf("SOno TIM2 Handler\n");
    ADC1->CR|=ADC_CR_ADSTART;
     //while((ADC1->ISR&ADC_ISR_EOC)!=ADC_ISR_EOC);
    j++;
    if(j==DIM_ADC){
        TIM2->CR1&=~TIM_CR1_CEN;

    }
}
void ADC1_2_IRQHandler(){
      printf("SOno Adc12 Handler\n");

    DMA1_Channel1->CCR|=DMA_CCR_EN;
    /* while((DMA1->ISR&DMA_ISR_TCIF1)!=DMA_ISR_TCIF1);
  DMA1->IFCR|=DMA_IFCR_CTCIF1;*/
}